This invention relates to a method for testing integrated circuit (IC) wafers for quality control of the process, and initial screening of IC devices prior to dicing and packaging the individual devices.
The use of microelectronic test structures for process characterization in IC fabrication is now common, usually in the form of inverters interspersed among the devices. Yet these structures often consume a lot of area on wafers and are considered an automatic yield loss. Concern about this area is a long standing one that has limited their use. In more recent times the shift from whole-wafer-lithography to direct-step-on-wafer lithography has placed further emphasis on the efficient utilization of wafer area for diagnostic purposes.
Test chips can be "pad intensive" where each test element in a test structure (such as a transistor) is connected to a separate probe pad. This approach to test chip layout has the advantage of eliminating the interference of one structure on another. The disadvantage of this approach is that only a limited number of structures can be sampled so that it may be difficult to establish a meaningful characterization of device parameters and process faults.